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caustino/processor

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1<!DOCTYPE html>2<html lang="en">3<head>4    <meta charset="UTF-8">5    <meta name="viewport" content="width=device-width, initial-scale=1.0">6    <title>HSPA Core Explorer</title>7    <link rel="icon" type="image/x-icon" href="/static/favicon.ico">8    <link rel="stylesheet" href="style.css">9    <script src="https://cdn.tailwindcss.com"></script>10    <script src="https://cdn.jsdelivr.net/npm/feather-icons/dist/feather.min.js"></script>11    <script src="https://unpkg.com/feather-icons"></script>12    <script src="https://cdn.jsdelivr.net/npm/vanta@latest/dist/vanta.globe.min.js"></script>13</head>14<body class="bg-gray-900 text-white min-h-screen flex flex-col">15    <custom-navbar></custom-navbar>16    17    <div id="vanta-bg" class="absolute inset-0 z-0"></div>18    19    <main class="relative z-10 flex-grow container mx-auto px-4 py-8">20        <section class="text-center py-16">21            <h1 class="text-5xl font-bold mb-6">HSPA Core Explorer</h1>22            <p class="text-xl max-w-2xl mx-auto mb-10">Dive into the next-generation Probabilistic Semantic Processing Architecture</p>23            <div class="flex justify-center gap-4">24                <a href="#architecture" class="bg-blue-600 hover:bg-blue-700 text-white font-bold py-3 px-6 rounded-lg transition duration-300">Explore Architecture</a>25                <a href="#prototype" class="bg-purple-600 hover:bg-purple-700 text-white font-bold py-3 px-6 rounded-lg transition duration-300">View Prototype</a>26            </div>27        </section>28 29        <section id="architecture" class="py-16">30            <h2 class="text-3xl font-bold mb-8 text-center">System Architecture</h2>31            <div class="grid grid-cols-1 md:grid-cols-2 lg:grid-cols-3 gap-8">32                <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">33                    <i data-feather="cpu" class="w-12 h-12 mb-4 text-blue-400"></i>34                    <h3 class="text-xl font-bold mb-2">PMCU</h3>35                    <p>Probabilistic Microcontroller Unit with Bayesian scheduling</p>36                </div>37                <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">38                    <i data-feather="grid" class="w-12 h-12 mb-4 text-green-400"></i>39                    <h3 class="text-xl font-bold mb-2">RLC Fabric</h3>40                    <p>Reconfigurable Logic Cell array for parallel execution</p>41                </div>42                <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">43                    <i data-feather="database" class="w-12 h-12 mb-4 text-yellow-400"></i>44                    <h3 class="text-xl font-bold mb-2">SEG Memory</h3>45                    <p>Semantic Execution Graph storage and management</p>46                </div>47                <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">48                    <i data-feather="layers" class="w-12 h-12 mb-4 text-red-400"></i>49                    <h3 class="text-xl font-bold mb-2">UML</h3>50                    <p>Unified Memory Lattice with semantic tagging</p>51                </div>52                <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">53                    <i data-feather="trending-up" class="w-12 h-12 mb-4 text-purple-400"></i>54                    <h3 class="text-xl font-bold mb-2">SOML</h3>55                    <p>Self-Optimizing Microcode Layer for adaptive performance</p>56                </div>57                <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm">58                    <i data-feather="refresh-cw" class="w-12 h-12 mb-4 text-indigo-400"></i>59                    <h3 class="text-xl font-bold mb-2">MIT</h3>60                    <p>Meta-ISA Translator for legacy compatibility</p>61                </div>62            </div>63        </section>64 65        <section id="prototype" class="py-16">66            <h2 class="text-3xl font-bold mb-8 text-center">Verilog Prototype</h2>67            <div class="bg-gray-800 bg-opacity-70 rounded-xl p-8 backdrop-blur-sm">68                <div class="flex flex-wrap gap-4 mb-6">69                    <button class="prototype-tab active" data-file="seg_memory.v">seg_memory.v</button>70                    <button class="prototype-tab" data-file="pmcu.v">pmcu.v</button>71                    <button class="prototype-tab" data-file="rlc.v">rlc.v</button>72                    <button class="prototype-tab" data-file="uml.v">uml.v</button>73                    <button class="prototype-tab" data-file="soml.v">soml.v</button>74                    <button class="prototype-tab" data-file="mit_translator.v">mit_translator.v</button>75                    <button class="prototype-tab" data-file="top.v">top.v</button>76                </div>77                <pre id="prototype-code" class="bg-gray-900 p-4 rounded-lg overflow-x-auto text-sm max-h-96"><code>// Loading prototype code...</code></pre>78            </div>79        </section>80 81        <section class="py-16">82            <h2 class="text-3xl font-bold mb-8 text-center">FPGA Carrier Board</h2>83            <div class="bg-gray-800 bg-opacity-70 rounded-xl p-8 backdrop-blur-sm">84                <div class="grid grid-cols-1 md:grid-cols-2 gap-8">85                    <div>86                        <h3 class="text-xl font-bold mb-4">Key Specifications</h3>87                        <ul class="space-y-2">88                            <li class="flex items-center">89                                <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i>90                                Xilinx Zynq UltraScale+ MPSoC ZU9EG91                            </li>92                            <li class="flex items-center">93                                <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i>94                                2x 72-bit DDR4 ECC banks (up to 4GB)95                            </li>96                            <li class="flex items-center">97                                <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i>98                                PCIe Gen3 x8 edge connector99                            </li>100                            <li class="flex items-center">101                                <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i>102                                2x SFP+ cages (10GbE)103                            </li>104                            <li class="flex items-center">105                                <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i>106                                FMC HPC connector for expansion107                            </li>108                        </ul>109                    </div>110                    <div>111                        <h3 class="text-xl font-bold mb-4">Features</h3>112                        <ul class="space-y-2">113                            <li class="flex items-center">114                                <i data-feather="check-circle" class="w-5 h-5 mr-2 text-blue-400"></i>115                                Partial reconfiguration support116                            </li>117                            <li class="flex items-center">118                                <i data-feather="check-circle" class="w-5 h-5 mr-2 text-blue-400"></i>119                                PMBus power management120                            </li>121                            <li class="flex items-center">122                                <i data-feather="check-circle" class="w-5 h-5 mr-2 text-blue-400"></i>123                                Si5345 clock generation124                            </li>125                            <li class="flex items-center">126                                <i data-feather="check-circle" class="w-5 h-5 mr-2 text-blue-400"></i>127                                Thermal management with fan control128                            </li>129                            <li class="flex items-center">130                                <i data-feather="check-circle" class="w-5 h-5 mr-2 text-blue-400"></i>131                                JTAG/UART debugging interface132                            </li>133                        </ul>134                    </div>135                </div>136            </div>137        </section>138    </main>139 140    <custom-footer></custom-footer>141    <script src="components/navbar.js"></script>142    <script src="components/footer.js"></script>143    <script src="script.js"></script>144    <script>feather.replace();</script>145</body>146</html>