Brunobkr/llama.cpp_AlgMor24_github

1/*2Language: Verilog3Author: Jon Evans <jon@craftyjon.com>4Contributors: Boone Severson <boone.severson@gmail.com>5Description: Verilog is a hardware description language used in electronic design automation to describe digital and mixed-signal systems. This highlighter supports Verilog and SystemVerilog through IEEE 1800-2012.6Website: http://www.verilog.com7Category: hardware8*/9 10function verilog(hljs) {11  const regex = hljs.regex;12  const KEYWORDS = {13    $pattern: /\$?[\w]+(\$[\w]+)*/,14    keyword: [15      "accept_on",16      "alias",17      "always",18      "always_comb",19      "always_ff",20      "always_latch",21      "and",22      "assert",23      "assign",24      "assume",25      "automatic",26      "before",27      "begin",28      "bind",29      "bins",30      "binsof",31      "bit",32      "break",33      "buf|0",34      "bufif0",35      "bufif1",36      "byte",37      "case",38      "casex",39      "casez",40      "cell",41      "chandle",42      "checker",43      "class",44      "clocking",45      "cmos",46      "config",47      "const",48      "constraint",49      "context",50      "continue",51      "cover",52      "covergroup",53      "coverpoint",54      "cross",55      "deassign",56      "default",57      "defparam",58      "design",59      "disable",60      "dist",61      "do",62      "edge",63      "else",64      "end",65      "endcase",66      "endchecker",67      "endclass",68      "endclocking",69      "endconfig",70      "endfunction",71      "endgenerate",72      "endgroup",73      "endinterface",74      "endmodule",75      "endpackage",76      "endprimitive",77      "endprogram",78      "endproperty",79      "endspecify",80      "endsequence",81      "endtable",82      "endtask",83      "enum",84      "event",85      "eventually",86      "expect",87      "export",88      "extends",89      "extern",90      "final",91      "first_match",92      "for",93      "force",94      "foreach",95      "forever",96      "fork",97      "forkjoin",98      "function",99      "generate|5",100      "genvar",101      "global",102      "highz0",103      "highz1",104      "if",105      "iff",106      "ifnone",107      "ignore_bins",108      "illegal_bins",109      "implements",110      "implies",111      "import",112      "incdir",113      "include",114      "initial",115      "inout",116      "input",117      "inside",118      "instance",119      "int",120      "integer",121      "interconnect",122      "interface",123      "intersect",124      "join",125      "join_any",126      "join_none",127      "large",128      "let",129      "liblist",130      "library",131      "local",132      "localparam",133      "logic",134      "longint",135      "macromodule",136      "matches",137      "medium",138      "modport",139      "module",140      "nand",141      "negedge",142      "nettype",143      "new",144      "nexttime",145      "nmos",146      "nor",147      "noshowcancelled",148      "not",149      "notif0",150      "notif1",151      "or",152      "output",153      "package",154      "packed",155      "parameter",156      "pmos",157      "posedge",158      "primitive",159      "priority",160      "program",161      "property",162      "protected",163      "pull0",164      "pull1",165      "pulldown",166      "pullup",167      "pulsestyle_ondetect",168      "pulsestyle_onevent",169      "pure",170      "rand",171      "randc",172      "randcase",173      "randsequence",174      "rcmos",175      "real",176      "realtime",177      "ref",178      "reg",179      "reject_on",180      "release",181      "repeat",182      "restrict",183      "return",184      "rnmos",185      "rpmos",186      "rtran",187      "rtranif0",188      "rtranif1",189      "s_always",190      "s_eventually",191      "s_nexttime",192      "s_until",193      "s_until_with",194      "scalared",195      "sequence",196      "shortint",197      "shortreal",198      "showcancelled",199      "signed",200      "small",201      "soft",202      "solve",203      "specify",204      "specparam",205      "static",206      "string",207      "strong",208      "strong0",209      "strong1",210      "struct",211      "super",212      "supply0",213      "supply1",214      "sync_accept_on",215      "sync_reject_on",216      "table",217      "tagged",218      "task",219      "this",220      "throughout",221      "time",222      "timeprecision",223      "timeunit",224      "tran",225      "tranif0",226      "tranif1",227      "tri",228      "tri0",229      "tri1",230      "triand",231      "trior",232      "trireg",233      "type",234      "typedef",235      "union",236      "unique",237      "unique0",238      "unsigned",239      "until",240      "until_with",241      "untyped",242      "use",243      "uwire",244      "var",245      "vectored",246      "virtual",247      "void",248      "wait",249      "wait_order",250      "wand",251      "weak",252      "weak0",253      "weak1",254      "while",255      "wildcard",256      "wire",257      "with",258      "within",259      "wor",260      "xnor",261      "xor"262    ],263    literal: [ 'null' ],264    built_in: [265      "$finish",266      "$stop",267      "$exit",268      "$fatal",269      "$error",270      "$warning",271      "$info",272      "$realtime",273      "$time",274      "$printtimescale",275      "$bitstoreal",276      "$bitstoshortreal",277      "$itor",278      "$signed",279      "$cast",280      "$bits",281      "$stime",282      "$timeformat",283      "$realtobits",284      "$shortrealtobits",285      "$rtoi",286      "$unsigned",287      "$asserton",288      "$assertkill",289      "$assertpasson",290      "$assertfailon",291      "$assertnonvacuouson",292      "$assertoff",293      "$assertcontrol",294      "$assertpassoff",295      "$assertfailoff",296      "$assertvacuousoff",297      "$isunbounded",298      "$sampled",299      "$fell",300      "$changed",301      "$past_gclk",302      "$fell_gclk",303      "$changed_gclk",304      "$rising_gclk",305      "$steady_gclk",306      "$coverage_control",307      "$coverage_get",308      "$coverage_save",309      "$set_coverage_db_name",310      "$rose",311      "$stable",312      "$past",313      "$rose_gclk",314      "$stable_gclk",315      "$future_gclk",316      "$falling_gclk",317      "$changing_gclk",318      "$display",319      "$coverage_get_max",320      "$coverage_merge",321      "$get_coverage",322      "$load_coverage_db",323      "$typename",324      "$unpacked_dimensions",325      "$left",326      "$low",327      "$increment",328      "$clog2",329      "$ln",330      "$log10",331      "$exp",332      "$sqrt",333      "$pow",334      "$floor",335      "$ceil",336      "$sin",337      "$cos",338      "$tan",339      "$countbits",340      "$onehot",341      "$isunknown",342      "$fatal",343      "$warning",344      "$dimensions",345      "$right",346      "$high",347      "$size",348      "$asin",349      "$acos",350      "$atan",351      "$atan2",352      "$hypot",353      "$sinh",354      "$cosh",355      "$tanh",356      "$asinh",357      "$acosh",358      "$atanh",359      "$countones",360      "$onehot0",361      "$error",362      "$info",363      "$random",364      "$dist_chi_square",365      "$dist_erlang",366      "$dist_exponential",367      "$dist_normal",368      "$dist_poisson",369      "$dist_t",370      "$dist_uniform",371      "$q_initialize",372      "$q_remove",373      "$q_exam",374      "$async$and$array",375      "$async$nand$array",376      "$async$or$array",377      "$async$nor$array",378      "$sync$and$array",379      "$sync$nand$array",380      "$sync$or$array",381      "$sync$nor$array",382      "$q_add",383      "$q_full",384      "$psprintf",385      "$async$and$plane",386      "$async$nand$plane",387      "$async$or$plane",388      "$async$nor$plane",389      "$sync$and$plane",390      "$sync$nand$plane",391      "$sync$or$plane",392      "$sync$nor$plane",393      "$system",394      "$display",395      "$displayb",396      "$displayh",397      "$displayo",398      "$strobe",399      "$strobeb",400      "$strobeh",401      "$strobeo",402      "$write",403      "$readmemb",404      "$readmemh",405      "$writememh",406      "$value$plusargs",407      "$dumpvars",408      "$dumpon",409      "$dumplimit",410      "$dumpports",411      "$dumpportson",412      "$dumpportslimit",413      "$writeb",414      "$writeh",415      "$writeo",416      "$monitor",417      "$monitorb",418      "$monitorh",419      "$monitoro",420      "$writememb",421      "$dumpfile",422      "$dumpoff",423      "$dumpall",424      "$dumpflush",425      "$dumpportsoff",426      "$dumpportsall",427      "$dumpportsflush",428      "$fclose",429      "$fdisplay",430      "$fdisplayb",431      "$fdisplayh",432      "$fdisplayo",433      "$fstrobe",434      "$fstrobeb",435      "$fstrobeh",436      "$fstrobeo",437      "$swrite",438      "$swriteb",439      "$swriteh",440      "$swriteo",441      "$fscanf",442      "$fread",443      "$fseek",444      "$fflush",445      "$feof",446      "$fopen",447      "$fwrite",448      "$fwriteb",449      "$fwriteh",450      "$fwriteo",451      "$fmonitor",452      "$fmonitorb",453      "$fmonitorh",454      "$fmonitoro",455      "$sformat",456      "$sformatf",457      "$fgetc",458      "$ungetc",459      "$fgets",460      "$sscanf",461      "$rewind",462      "$ftell",463      "$ferror"464    ]465  };466  const BUILT_IN_CONSTANTS = [467    "__FILE__",468    "__LINE__"469  ];470  const DIRECTIVES = [471    "begin_keywords",472    "celldefine",473    "default_nettype",474    "default_decay_time",475    "default_trireg_strength",476    "define",477    "delay_mode_distributed",478    "delay_mode_path",479    "delay_mode_unit",480    "delay_mode_zero",481    "else",482    "elsif",483    "end_keywords",484    "endcelldefine",485    "endif",486    "ifdef",487    "ifndef",488    "include",489    "line",490    "nounconnected_drive",491    "pragma",492    "resetall",493    "timescale",494    "unconnected_drive",495    "undef",496    "undefineall"497  ];498 499  return {500    name: 'Verilog',501    aliases: [502      'v',503      'sv',504      'svh'505    ],506    case_insensitive: false,507    keywords: KEYWORDS,508    contains: [509      hljs.C_BLOCK_COMMENT_MODE,510      hljs.C_LINE_COMMENT_MODE,511      hljs.QUOTE_STRING_MODE,512      {513        scope: 'number',514        contains: [ hljs.BACKSLASH_ESCAPE ],515        variants: [516          { begin: /\b((\d+'([bhodBHOD]))[0-9xzXZa-fA-F_]+)/ },517          { begin: /\B(('([bhodBHOD]))[0-9xzXZa-fA-F_]+)/ },518          { // decimal519            begin: /\b[0-9][0-9_]*/,520            relevance: 0521          }522        ]523      },524      /* parameters to instances */525      {526        scope: 'variable',527        variants: [528          { begin: '#\\((?!parameter).+\\)' },529          {530            begin: '\\.\\w+',531            relevance: 0532          }533        ]534      },535      {536        scope: 'variable.constant',537        match: regex.concat(/`/, regex.either(...BUILT_IN_CONSTANTS)),538      },539      {540        scope: 'meta',541        begin: regex.concat(/`/, regex.either(...DIRECTIVES)),542        end: /$|\/\/|\/\*/,543        returnEnd: true,544        keywords: DIRECTIVES545      }546    ]547  };548}549 550module.exports = verilog;551