codekingpro/portable-devtools

1" Vim syntax file2" Language:	Verilog3" Maintainer:	Mun Johl <Mun.Johl@emulex.com>4" Last Update:  Wed Jul 20 16:04:19 PDT 20115 6" quit when a syntax file was already loaded7if exists("b:current_syntax")8   finish9endif10 11" Set the local value of the 'iskeyword' option.12" NOTE: '?' was added so that verilogNumber would be processed correctly when13"       '?' is the last character of the number.14setlocal iskeyword=@,48-57,63,_,192-25515 16" A bunch of useful Verilog keywords17 18syn keyword verilogStatement   always and assign automatic buf19syn keyword verilogStatement   bufif0 bufif1 cell cmos20syn keyword verilogStatement   config deassign defparam design21syn keyword verilogStatement   disable edge endconfig22syn keyword verilogStatement   endfunction endgenerate endmodule23syn keyword verilogStatement   endprimitive endspecify endtable endtask24syn keyword verilogStatement   event force function25syn keyword verilogStatement   generate genvar highz0 highz1 ifnone26syn keyword verilogStatement   incdir include initial inout input27syn keyword verilogStatement   instance integer large liblist28syn keyword verilogStatement   library localparam macromodule medium29syn keyword verilogStatement   module nand negedge nmos nor30syn keyword verilogStatement   noshowcancelled not notif0 notif1 or31syn keyword verilogStatement   output parameter pmos posedge primitive32syn keyword verilogStatement   pull0 pull1 pulldown pullup33syn keyword verilogStatement   pulsestyle_onevent pulsestyle_ondetect34syn keyword verilogStatement   rcmos real realtime reg release35syn keyword verilogStatement   rnmos rpmos rtran rtranif0 rtranif136syn keyword verilogStatement   scalared showcancelled signed small37syn keyword verilogStatement   specify specparam strong0 strong138syn keyword verilogStatement   supply0 supply1 table task time tran39syn keyword verilogStatement   tranif0 tranif1 tri tri0 tri1 triand40syn keyword verilogStatement   trior trireg unsigned use vectored wait41syn keyword verilogStatement   wand weak0 weak1 wire wor xnor xor42syn keyword verilogLabel       begin end fork join43syn keyword verilogConditional if else case casex casez default endcase44syn keyword verilogRepeat      forever repeat while for45 46syn keyword verilogTodo contained TODO FIXME47 48syn match   verilogOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]"49 50syn region  verilogComment start="/\*" end="\*/" contains=verilogTodo,@Spell51syn match   verilogComment "//.*" contains=verilogTodo,@Spell52 53"syn match   verilogGlobal "`[a-zA-Z0-9_]\+\>"54syn match verilogGlobal "`celldefine"55syn match verilogGlobal "`default_nettype"56syn match verilogGlobal "`define"57syn match verilogGlobal "`else"58syn match verilogGlobal "`elsif"59syn match verilogGlobal "`endcelldefine"60syn match verilogGlobal "`endif"61syn match verilogGlobal "`ifdef"62syn match verilogGlobal "`ifndef"63syn match verilogGlobal "`include"64syn match verilogGlobal "`line"65syn match verilogGlobal "`nounconnected_drive"66syn match verilogGlobal "`resetall"67syn match verilogGlobal "`timescale"68syn match verilogGlobal "`unconnected_drive"69syn match verilogGlobal "`undef"70syn match   verilogGlobal "$[a-zA-Z0-9_]\+\>"71 72syn match   verilogConstant "\<[A-Z][A-Z0-9_]\+\>"73 74syn match   verilogNumber "\(\<\d\+\|\)'[sS]\?[bB]\s*[0-1_xXzZ?]\+\>"75syn match   verilogNumber "\(\<\d\+\|\)'[sS]\?[oO]\s*[0-7_xXzZ?]\+\>"76syn match   verilogNumber "\(\<\d\+\|\)'[sS]\?[dD]\s*[0-9_xXzZ?]\+\>"77syn match   verilogNumber "\(\<\d\+\|\)'[sS]\?[hH]\s*[0-9a-fA-F_xXzZ?]\+\>"78syn match   verilogNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)\>"79 80syn region  verilogString start=+"+ skip=+\\"+ end=+"+ contains=verilogEscape,@Spell81syn match   verilogEscape +\\[nt"\\]+ contained82syn match   verilogEscape "\\\o\o\=\o\=" contained83 84" Directives85syn match   verilogDirective   "//\s*synopsys\>.*$"86syn region  verilogDirective   start="/\*\s*synopsys\>" end="\*/"87syn region  verilogDirective   start="//\s*synopsys dc_script_begin\>" end="//\s*synopsys dc_script_end\>"88 89syn match   verilogDirective   "//\s*\$s\>.*$"90syn region  verilogDirective   start="/\*\s*\$s\>" end="\*/"91syn region  verilogDirective   start="//\s*\$s dc_script_begin\>" end="//\s*\$s dc_script_end\>"92 93"Modify the following as needed.  The trade-off is performance versus94"functionality.95syn sync minlines=5096 97" Define the default highlighting.98" Only when an item doesn't have highlighting yet99 100" The default highlighting.101hi def link verilogCharacter       Character102hi def link verilogConditional     Conditional103hi def link verilogRepeat          Repeat104hi def link verilogString          String105hi def link verilogTodo            Todo106hi def link verilogComment         Comment107hi def link verilogConstant        Constant108hi def link verilogLabel           Label109hi def link verilogNumber          Number110hi def link verilogOperator        Special111hi def link verilogStatement       Statement112hi def link verilogGlobal          Define113hi def link verilogDirective       SpecialComment114hi def link verilogEscape		 Special115 116 117let b:current_syntax = "verilog"118 119" vim: ts=8120