codekingpro/portable-devtools

1" Vim syntax file2" Language:    Verilog-AMS3" Maintainer:  S. Myles Prather <smprather@gmail.com>4"5" Version 1.1  S. Myles Prather <smprather@gmail.com>6"              Moved some keywords to the type category.7"              Added the metrix suffixes to the number matcher.8" Version 1.2  Prasanna Tamhankar <pratam@gmail.com>9"              Minor reserved keyword updates.10" Last Update: Thursday September 15 15:36:03 CST 2005 11 12" quit when a syntax file was already loaded13if exists("b:current_syntax")14   finish15endif16 17" Set the local value of the 'iskeyword' option18setlocal iskeyword=@,48-57,_,192-25519 20" Annex B.1 'All keywords'21syn keyword verilogamsStatement above abs absdelay acos acosh ac_stim22syn keyword verilogamsStatement always analog analysis and asin23syn keyword verilogamsStatement asinh assign atan atan2 atanh24syn keyword verilogamsStatement buf bufif0 bufif1 ceil cmos connectmodule25syn keyword verilogamsStatement connectrules cos cosh cross ddt ddx deassign26syn keyword verilogamsStatement defparam disable discipline27syn keyword verilogamsStatement driver_update edge enddiscipline28syn keyword verilogamsStatement endconnectrules endmodule endfunction endgenerate29syn keyword verilogamsStatement endnature endparamset endprimitive endspecify30syn keyword verilogamsStatement endtable endtask event exp final_step31syn keyword verilogamsStatement flicker_noise floor flow force fork32syn keyword verilogamsStatement function generate highz033syn keyword verilogamsStatement highz1 hypot idt idtmod if ifnone inf initial34syn keyword verilogamsStatement initial_step inout input join35syn keyword verilogamsStatement laplace_nd laplace_np laplace_zd laplace_zp36syn keyword verilogamsStatement large last_crossing limexp ln localparam log37syn keyword verilogamsStatement macromodule max medium min module nand nature38syn keyword verilogamsStatement negedge net_resolution nmos noise_table nor not39syn keyword verilogamsStatement notif0 notif1 or output paramset pmos40syn keyword verilogamsType      parameter real integer electrical input output41syn keyword verilogamsType      inout reg tri tri0 tri1 triand trior trireg42syn keyword verilogamsType      string from exclude aliasparam ground genvar43syn keyword verilogamsType      branch time realtime44syn keyword verilogamsStatement posedge potential pow primitive pull0 pull145syn keyword verilogamsStatement pullup pulldown rcmos release46syn keyword verilogamsStatement rnmos rpmos rtran rtranif0 rtranif147syn keyword verilogamsStatement scalared sin sinh slew small specify specparam48syn keyword verilogamsStatement sqrt strong0 strong1 supply0 supply149syn keyword verilogamsStatement table tan tanh task timer tran tranif050syn keyword verilogamsStatement tranif1 transition51syn keyword verilogamsStatement vectored wait wand weak0 weak152syn keyword verilogamsStatement white_noise wire wor wreal xnor xor zi_nd53syn keyword verilogamsStatement zi_np zi_zd zi_zp54syn keyword verilogamsRepeat    forever repeat while for55syn keyword verilogamsLabel     begin end56syn keyword verilogamsConditional if else case casex casez default endcase57syn match   verilogamsConstant  ":inf"lc=158syn match   verilogamsConstant  "-inf"lc=159" Annex B.2 Discipline/nature60syn keyword verilogamsStatement abstol access continuous ddt_nature discrete61syn keyword verilogamsStatement domain idt_nature units 62" Annex B.3 Connect Rules63syn keyword verilogamsStatement connect merged resolveto split64 65syn match   verilogamsOperator  "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]"66syn match   verilogamsOperator  "<+"67syn match   verilogamsStatement "[vV]("me=e-168syn match   verilogamsStatement "[iI]("me=e-169 70syn keyword verilogamsTodo contained TODO71syn region  verilogamsComment start="/\*" end="\*/" contains=verilogamsTodo72syn match   verilogamsComment "//.*" contains=verilogamsTodo73 74syn match verilogamsGlobal "`celldefine"75syn match verilogamsGlobal "`default_nettype"76syn match verilogamsGlobal "`define"77syn match verilogamsGlobal "`else"78syn match verilogamsGlobal "`elsif"79syn match verilogamsGlobal "`endcelldefine"80syn match verilogamsGlobal "`endif"81syn match verilogamsGlobal "`ifdef"82syn match verilogamsGlobal "`ifndef"83syn match verilogamsGlobal "`include"84syn match verilogamsGlobal "`line"85syn match verilogamsGlobal "`nounconnected_drive"86syn match verilogamsGlobal "`resetall"87syn match verilogamsGlobal "`timescale"88syn match verilogamsGlobal "`unconnected_drive"89syn match verilogamsGlobal "`undef"90syn match verilogamsSystask "$[a-zA-Z0-9_]\+\>"91 92syn match verilogamsConstant "\<[A-Z][A-Z0-9_]\+\>"93 94syn match   verilogamsNumber "\(\<\d\+\|\)'[bB]\s*[0-1_xXzZ?]\+\>"95syn match   verilogamsNumber "\(\<\d\+\|\)'[oO]\s*[0-7_xXzZ?]\+\>"96syn match   verilogamsNumber "\(\<\d\+\|\)'[dD]\s*[0-9_xXzZ?]\+\>"97syn match   verilogamsNumber "\(\<\d\+\|\)'[hH]\s*[0-9a-fA-F_xXzZ?]\+\>"98syn match   verilogamsNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)[TGMKkmunpfa]\=\>"99 100syn region  verilogamsString start=+"+ skip=+\\"+ end=+"+ contains=verilogamsEscape101syn match   verilogamsEscape +\\[nt"\\]+ contained102syn match   verilogamsEscape "\\\o\o\=\o\=" contained103 104"Modify the following as needed.  The trade-off is performance versus105"functionality.106syn sync lines=50107 108" Define the default highlighting.109" Only when an item doesn't have highlighting yet110 111" The default highlighting.112hi def link verilogamsCharacter    Character113hi def link verilogamsConditional  Conditional114hi def link verilogamsRepeat       Repeat115hi def link verilogamsString       String116hi def link verilogamsTodo         Todo117hi def link verilogamsComment      Comment118hi def link verilogamsConstant     Constant119hi def link verilogamsLabel        Label120hi def link verilogamsNumber       Number121hi def link verilogamsOperator     Special122hi def link verilogamsStatement    Statement123hi def link verilogamsGlobal       Define124hi def link verilogamsDirective    SpecialComment125hi def link verilogamsEscape       Special126hi def link verilogamsType         Type127hi def link verilogamsSystask      Function128 129 130let b:current_syntax = "verilogams"131 132" vim: ts=8133