codekingpro/portable-devtools

1// asmcheck2 3// Copyright 2018 The Go Authors. All rights reserved.4// Use of this source code is governed by a BSD-style5// license that can be found in the LICENSE file.6 7package codegen8 9// ------------------ //10//   constant shifts  //11// ------------------ //12 13func lshConst64x64(v int64) int64 {14	// loong64:"SLLV"15	// ppc64x:"SLD"16	// riscv64:"SLLI" -"AND" -"SLTIU"17	return v << uint64(33)18}19 20func rshConst64Ux64(v uint64) uint64 {21	// loong64:"SRLV"22	// ppc64x:"SRD"23	// riscv64:"SRLI " -"AND" -"SLTIU"24	return v >> uint64(33)25}26 27func rshConst64Ux64Overflow32(v uint32) uint64 {28	// loong64:"MOVV R0," -"SRL "29	// riscv64:"MOV [$]0," -"SRL"30	return uint64(v) >> 3231}32 33func rshConst64Ux64Overflow16(v uint16) uint64 {34	// loong64:"MOVV R0," -"SRLV"35	// riscv64:"MOV [$]0," -"SRL"36	return uint64(v) >> 1637}38 39func rshConst64Ux64Overflow8(v uint8) uint64 {40	// loong64:"MOVV R0," -"SRLV"41	// riscv64:"MOV [$]0," -"SRL"42	return uint64(v) >> 843}44 45func rshConst64x64(v int64) int64 {46	// loong64:"SRAV"47	// ppc64x:"SRAD"48	// riscv64:"SRAI " -"OR" -"SLTIU"49	return v >> uint64(33)50}51 52func rshConst64x64Overflow32(v int32) int64 {53	// loong64:"SRA [$]31"54	// riscv64:"SRAIW" -"SLLI" -"SRAI "55	return int64(v) >> 3256}57 58func rshConst64x64Overflow16(v int16) int64 {59	// loong64:"SLLV [$]48" "SRAV [$]63"60	// riscv64:"SLLI" "SRAI" -"SRAIW"61	return int64(v) >> 1662}63 64func rshConst64x64Overflow8(v int8) int64 {65	// loong64:"SLLV [$]56" "SRAV [$]63"66	// riscv64:"SLLI" "SRAI" -"SRAIW"67	return int64(v) >> 868}69 70func lshConst32x1(v int32) int32 {71	// amd64:"ADDL", -"SHLL"72	return v << 173}74 75func lshConst64x1(v int64) int64 {76	// amd64:"ADDQ", -"SHLQ"77	return v << 178}79 80func lshConst32x64(v int32) int32 {81	// loong64:"SLL "82	// ppc64x:"SLW"83	// riscv64:"SLLI" -"AND" -"SLTIU", -"MOVW"84	return v << uint64(29)85}86 87func rshConst32Ux64(v uint32) uint32 {88	// loong64:"SRL "89	// ppc64x:"SRW"90	// riscv64:"SRLIW" -"AND" -"SLTIU", -"MOVW"91	return v >> uint64(29)92}93 94func rshConst32x64(v int32) int32 {95	// loong64:"SRA "96	// ppc64x:"SRAW"97	// riscv64:"SRAIW" -"OR" -"SLTIU", -"MOVW"98	return v >> uint64(29)99}100 101func lshConst64x32(v int64) int64 {102	// loong64:"SLLV"103	// ppc64x:"SLD"104	// riscv64:"SLLI" -"AND" -"SLTIU"105	return v << uint32(33)106}107 108func rshConst64Ux32(v uint64) uint64 {109	// loong64:"SRLV"110	// ppc64x:"SRD"111	// riscv64:"SRLI " -"AND" -"SLTIU"112	return v >> uint32(33)113}114 115func rshConst64x32(v int64) int64 {116	// loong64:"SRAV"117	// ppc64x:"SRAD"118	// riscv64:"SRAI " -"OR" -"SLTIU"119	return v >> uint32(33)120}121 122func lshConst32x1Add(x int32) int32 {123	// amd64:"SHLL [$]2"124	// loong64:"SLL [$]2"125	// riscv64:"SLLI [$]2"126	return (x + x) << 1127}128 129func lshConst64x1Add(x int64) int64 {130	// amd64:"SHLQ [$]2"131	// loong64:"SLLV [$]2"132	// riscv64:"SLLI [$]2"133	return (x + x) << 1134}135 136func lshConst32x2Add(x int32) int32 {137	// amd64:"SHLL [$]3"138	// loong64:"SLL [$]3"139	// riscv64:"SLLI [$]3"140	return (x + x) << 2141}142 143func lshConst64x2Add(x int64) int64 {144	// amd64:"SHLQ [$]3"145	// loong64:"SLLV [$]3"146	// riscv64:"SLLI [$]3"147	return (x + x) << 2148}149 150func lshConst32x31Add(x int32) int32 {151	// loong64:-"SLL " "MOVV R0"152	// riscv64:-"SLLI" "MOV [$]0"153	return (x + x) << 31154}155 156func lshConst64x63Add(x int64) int64 {157	// loong64:-"SLLV" "MOVV R0"158	// riscv64:-"SLLI" "MOV [$]0"159	return (x + x) << 63160}161 162// ------------------ //163//   masked shifts    //164// ------------------ //165 166func lshMask64x64(v int64, s uint64) int64 {167	// arm64:"LSL" -"AND"168	// loong64:"SLLV" -"AND"169	// ppc64x:"RLDICL" -"ORN" -"ISEL"170	// riscv64:"SLL" -"AND " -"SLTIU"171	// s390x:-"RISBGZ" -"AND" -"LOCGR"172	return v << (s & 63)173}174 175func rshMask64Ux64(v uint64, s uint64) uint64 {176	// arm64:"LSR" -"AND" -"CSEL"177	// loong64:"SRLV" -"AND"178	// ppc64x:"RLDICL" -"ORN" -"ISEL"179	// riscv64:"SRL " -"AND " -"SLTIU"180	// s390x:-"RISBGZ" -"AND" -"LOCGR"181	return v >> (s & 63)182}183 184func rshMask64x64(v int64, s uint64) int64 {185	// arm64:"ASR" -"AND" -"CSEL"186	// loong64:"SRAV" -"AND"187	// ppc64x:"RLDICL" -"ORN" -"ISEL"188	// riscv64:"SRA " -"OR" -"SLTIU"189	// s390x:-"RISBGZ" -"AND" -"LOCGR"190	return v >> (s & 63)191}192 193func lshMask32x64(v int32, s uint64) int32 {194	// arm64:"LSL" -"AND"195	// loong64:"SLL " "AND" "SGTU" "MASKEQZ"196	// ppc64x:"ISEL" -"ORN"197	// riscv64:"SLL" -"AND " -"SLTIU"198	// s390x:-"RISBGZ" -"AND" -"LOCGR"199	return v << (s & 63)200}201 202func lsh5Mask32x64(v int32, s uint64) int32 {203	// loong64:"SLL " -"AND"204	return v << (s & 31)205}206 207func rshMask32Ux64(v uint32, s uint64) uint32 {208	// arm64:"LSR" -"AND"209	// loong64:"SRL " "AND" "SGTU" "MASKEQZ"210	// ppc64x:"ISEL" -"ORN"211	// riscv64:"SRLW" "SLTIU" "NEG" "AND " -"SRL "212	// s390x:-"RISBGZ" -"AND" -"LOCGR"213	return v >> (s & 63)214}215 216func rsh5Mask32Ux64(v uint32, s uint64) uint32 {217	// loong64:"SRL " -"AND"218	// riscv64:"SRLW" -"AND " -"SLTIU" -"SRL "219	return v >> (s & 31)220}221 222func rshMask32x64(v int32, s uint64) int32 {223	// arm64:"ASR" -"AND"224	// loong64:"SRA " "AND" "SGTU" "SUBVU" "OR"225	// ppc64x:"ISEL" -"ORN"226	// riscv64:"SRAW" "OR" "SLTIU"227	// s390x:-"RISBGZ" -"AND" -"LOCGR"228	return v >> (s & 63)229}230 231func rsh5Mask32x64(v int32, s uint64) int32 {232	// loong64:"SRA " -"AND"233	// riscv64:"SRAW" -"OR" -"SLTIU"234	return v >> (s & 31)235}236 237func lshMask64x32(v int64, s uint32) int64 {238	// arm64:"LSL" -"AND"239	// loong64:"SLLV" -"AND"240	// ppc64x:"RLDICL" -"ORN"241	// riscv64:"SLL" -"AND " -"SLTIU"242	// s390x:-"RISBGZ" -"AND" -"LOCGR"243	return v << (s & 63)244}245 246func rshMask64Ux32(v uint64, s uint32) uint64 {247	// arm64:"LSR" -"AND" -"CSEL"248	// loong64:"SRLV" -"AND"249	// ppc64x:"RLDICL" -"ORN"250	// riscv64:"SRL " -"AND " -"SLTIU"251	// s390x:-"RISBGZ" -"AND" -"LOCGR"252	return v >> (s & 63)253}254 255func rshMask64x32(v int64, s uint32) int64 {256	// arm64:"ASR" -"AND" -"CSEL"257	// loong64:"SRAV" -"AND"258	// ppc64x:"RLDICL" -"ORN" -"ISEL"259	// riscv64:"SRA " -"OR" -"SLTIU"260	// s390x:-"RISBGZ" -"AND" -"LOCGR"261	return v >> (s & 63)262}263 264func lshMask64x32Ext(v int64, s int32) int64 {265	// ppc64x:"RLDICL" -"ORN" -"ISEL"266	// riscv64:"SLL" -"AND " -"SLTIU"267	// s390x:-"RISBGZ" -"AND" -"LOCGR"268	return v << uint(s&63)269}270 271func rshMask64Ux32Ext(v uint64, s int32) uint64 {272	// ppc64x:"RLDICL" -"ORN" -"ISEL"273	// riscv64:"SRL " -"AND " -"SLTIU"274	// s390x:-"RISBGZ" -"AND" -"LOCGR"275	return v >> uint(s&63)276}277 278func rshMask64x32Ext(v int64, s int32) int64 {279	// ppc64x:"RLDICL" -"ORN" -"ISEL"280	// riscv64:"SRA " -"OR" -"SLTIU"281	// s390x:-"RISBGZ" -"AND" -"LOCGR"282	return v >> uint(s&63)283}284 285// --------------- //286//  signed shifts  //287// --------------- //288 289// We do want to generate a test + panicshift for these cases.290func lshSigned(v8 int8, v16 int16, v32 int32, v64 int64, x int) {291	// amd64:"TESTB"292	_ = x << v8293	// amd64:"TESTW"294	_ = x << v16295	// amd64:"TESTL"296	_ = x << v32297	// amd64:"TESTQ"298	_ = x << v64299}300 301// We want to avoid generating a test + panicshift for these cases.302func lshSignedMasked(v8 int8, v16 int16, v32 int32, v64 int64, x int) {303	// amd64:-"TESTB"304	_ = x << (v8 & 7)305	// amd64:-"TESTW"306	_ = x << (v16 & 15)307	// amd64:-"TESTL"308	_ = x << (v32 & 31)309	// amd64:-"TESTQ"310	_ = x << (v64 & 63)311}312 313// ------------------ //314//   bounded shifts   //315// ------------------ //316 317func lshGuarded64(v int64, s uint) int64 {318	if s < 64 {319		// riscv64:"SLL" -"AND" -"SLTIU"320		// s390x:-"RISBGZ" -"AND" -"LOCGR"321		// wasm:-"Select" -".*LtU"322		// arm64:"LSL" -"CSEL"323		return v << s324	}325	panic("shift too large")326}327 328func rshGuarded64U(v uint64, s uint) uint64 {329	if s < 64 {330		// riscv64:"SRL " -"AND" -"SLTIU"331		// s390x:-"RISBGZ" -"AND" -"LOCGR"332		// wasm:-"Select" -".*LtU"333		// arm64:"LSR" -"CSEL"334		return v >> s335	}336	panic("shift too large")337}338 339func rshGuarded64(v int64, s uint) int64 {340	if s < 64 {341		// riscv64:"SRA " -"OR" -"SLTIU"342		// s390x:-"RISBGZ" -"AND" -"LOCGR"343		// wasm:-"Select" -".*LtU"344		// arm64:"ASR" -"CSEL"345		return v >> s346	}347	panic("shift too large")348}349 350func provedUnsignedShiftLeft(val64 uint64, val32 uint32, val16 uint16, val8 uint8, shift int) (r1 uint64, r2 uint32, r3 uint16, r4 uint8) {351	if shift >= 0 && shift < 64 {352		// arm64:"LSL" -"CSEL"353		r1 = val64 << shift354	}355	if shift >= 0 && shift < 32 {356		// arm64:"LSL" -"CSEL"357		r2 = val32 << shift358	}359	if shift >= 0 && shift < 16 {360		// arm64:"LSL" -"CSEL"361		r3 = val16 << shift362	}363	if shift >= 0 && shift < 8 {364		// arm64:"LSL" -"CSEL"365		r4 = val8 << shift366	}367	return r1, r2, r3, r4368}369 370func provedSignedShiftLeft(val64 int64, val32 int32, val16 int16, val8 int8, shift int) (r1 int64, r2 int32, r3 int16, r4 int8) {371	if shift >= 0 && shift < 64 {372		// arm64:"LSL" -"CSEL"373		r1 = val64 << shift374	}375	if shift >= 0 && shift < 32 {376		// arm64:"LSL" -"CSEL"377		r2 = val32 << shift378	}379	if shift >= 0 && shift < 16 {380		// arm64:"LSL" -"CSEL"381		r3 = val16 << shift382	}383	if shift >= 0 && shift < 8 {384		// arm64:"LSL" -"CSEL"385		r4 = val8 << shift386	}387	return r1, r2, r3, r4388}389 390func provedUnsignedShiftRight(val64 uint64, val32 uint32, val16 uint16, val8 uint8, shift int) (r1 uint64, r2 uint32, r3 uint16, r4 uint8) {391	if shift >= 0 && shift < 64 {392		// arm64:"LSR" -"CSEL"393		r1 = val64 >> shift394	}395	if shift >= 0 && shift < 32 {396		// arm64:"LSR" -"CSEL"397		r2 = val32 >> shift398	}399	if shift >= 0 && shift < 16 {400		// arm64:"LSR" -"CSEL"401		r3 = val16 >> shift402	}403	if shift >= 0 && shift < 8 {404		// arm64:"LSR" -"CSEL"405		r4 = val8 >> shift406	}407	return r1, r2, r3, r4408}409 410func provedSignedShiftRight(val64 int64, val32 int32, val16 int16, val8 int8, shift int) (r1 int64, r2 int32, r3 int16, r4 int8) {411	if shift >= 0 && shift < 64 {412		// arm64:"ASR" -"CSEL"413		r1 = val64 >> shift414	}415	if shift >= 0 && shift < 32 {416		// arm64:"ASR" -"CSEL"417		r2 = val32 >> shift418	}419	if shift >= 0 && shift < 16 {420		// arm64:"ASR" -"CSEL"421		r3 = val16 >> shift422	}423	if shift >= 0 && shift < 8 {424		// arm64:"ASR" -"CSEL"425		r4 = val8 >> shift426	}427	return r1, r2, r3, r4428}429 430func checkUnneededTrunc(tab *[100000]uint32, d uint64, v uint32, h uint16, b byte) (uint32, uint64) {431 432	// ppc64x:-".*RLWINM" -".*RLDICR" ".*CLRLSLDI"433	f := tab[byte(v)^b]434	// ppc64x:-".*RLWINM" -".*RLDICR" ".*CLRLSLDI"435	f += tab[byte(v)&b]436	// ppc64x:-".*RLWINM" -".*RLDICR" ".*CLRLSLDI"437	f += tab[byte(v)|b]438	// ppc64x:-".*RLWINM" -".*RLDICR" ".*CLRLSLDI"439	f += tab[uint16(v)&h]440	// ppc64x:-".*RLWINM" -".*RLDICR" ".*CLRLSLDI"441	f += tab[uint16(v)^h]442	// ppc64x:-".*RLWINM" -".*RLDICR" ".*CLRLSLDI"443	f += tab[uint16(v)|h]444	// ppc64x:-".*AND" -"RLDICR" ".*CLRLSLDI"445	f += tab[v&0xff]446	// ppc64x:-".*AND" ".*CLRLSLWI"447	f += 2 * uint32(uint16(d))448	// ppc64x:-".*AND" -"RLDICR" ".*CLRLSLDI"449	g := 2 * uint64(uint32(d))450	return f, g451}452 453func checkCombinedShifts(v8 uint8, v16 uint16, v32 uint32, x32 int32, v64 uint64) (uint8, uint16, uint32, uint64, int64) {454 455	// ppc64x:-"AND" "CLRLSLWI"456	f := (v8 & 0xF) << 2457	// ppc64x:"CLRLSLWI"458	f += byte(v16) << 3459	// ppc64x:-"AND" "CLRLSLWI"460	g := (v16 & 0xFF) << 3461	// ppc64x:-"AND" "CLRLSLWI"462	h := (v32 & 0xFFFFF) << 2463	// ppc64x:"CLRLSLDI"464	i := (v64 & 0xFFFFFFFF) << 5465	// ppc64x:-"CLRLSLDI"466	i += (v64 & 0xFFFFFFF) << 38467	// ppc64x/power9:-"CLRLSLDI"468	i += (v64 & 0xFFFF00) << 10469	// ppc64x/power9:-"SLD" "EXTSWSLI"470	j := int64(x32+32) * 8471	return f, g, h, i, j472}473 474func checkWidenAfterShift(v int64, u uint64) (int64, uint64) {475 476	// ppc64x:-".*MOVW"477	f := int32(v >> 32)478	// ppc64x:".*MOVW"479	f += int32(v >> 31)480	// ppc64x:-".*MOVH"481	g := int16(v >> 48)482	// ppc64x:".*MOVH"483	g += int16(v >> 30)484	// ppc64x:-".*MOVH"485	g += int16(f >> 16)486	// ppc64x:-".*MOVB"487	h := int8(v >> 56)488	// ppc64x:".*MOVB"489	h += int8(v >> 28)490	// ppc64x:-".*MOVB"491	h += int8(f >> 24)492	// ppc64x:".*MOVB"493	h += int8(f >> 16)494	return int64(h), uint64(g)495}496 497func checkShiftAndMask32(v []uint32) {498	i := 0499 500	// ppc64x: "RLWNM [$]24, R[0-9]+, [$]12, [$]19, R[0-9]+"501	v[i] = (v[i] & 0xFF00000) >> 8502	i++503	// ppc64x: "RLWNM [$]26, R[0-9]+, [$]22, [$]29, R[0-9]+"504	v[i] = (v[i] & 0xFF00) >> 6505	i++506	// ppc64x: "MOVW R0"507	v[i] = (v[i] & 0xFF) >> 8508	i++509	// ppc64x: "MOVW R0"510	v[i] = (v[i] & 0xF000000) >> 28511	i++512	// ppc64x: "RLWNM [$]26, R[0-9]+, [$]24, [$]31, R[0-9]+"513	v[i] = (v[i] >> 6) & 0xFF514	i++515	// ppc64x: "RLWNM [$]26, R[0-9]+, [$]12, [$]19, R[0-9]+"516	v[i] = (v[i] >> 6) & 0xFF000517	i++518	// ppc64x: "MOVW R0"519	v[i] = (v[i] >> 20) & 0xFF000520	i++521	// ppc64x: "MOVW R0"522	v[i] = (v[i] >> 24) & 0xFF00523	i++524}525 526func checkMergedShifts32(a [256]uint32, b [256]uint64, u uint32, v uint32) {527	// ppc64x: -"CLRLSLDI", "RLWNM [$]10, R[0-9]+, [$]22, [$]29, R[0-9]+"528	a[0] = a[uint8(v>>24)]529	// ppc64x: -"CLRLSLDI", "RLWNM [$]11, R[0-9]+, [$]21, [$]28, R[0-9]+"530	b[0] = b[uint8(v>>24)]531	// ppc64x: -"CLRLSLDI", "RLWNM [$]15, R[0-9]+, [$]21, [$]28, R[0-9]+"532	b[1] = b[(v>>20)&0xFF]533	// ppc64x: -"SLD", "RLWNM [$]10, R[0-9]+, [$]22, [$]28, R[0-9]+"534	b[2] = b[v>>25]535}536 537func checkMergedShifts64(a [256]uint32, b [256]uint64, c [256]byte, v uint64) {538	// ppc64x: -"CLRLSLDI", "RLWNM [$]10, R[0-9]+, [$]22, [$]29, R[0-9]+"539	a[0] = a[uint8(v>>24)]540	// ppc64x: "SRD", "CLRLSLDI", -"RLWNM"541	a[1] = a[uint8(v>>25)]542	// ppc64x: -"CLRLSLDI", "RLWNM [$]9, R[0-9]+, [$]23, [$]29, R[0-9]+"543	a[2] = a[v>>25&0x7F]544	// ppc64x: -"CLRLSLDI", "RLWNM [$]3, R[0-9]+, [$]29, [$]29, R[0-9]+"545	a[3] = a[(v>>31)&0x01]546	// ppc64x: -"CLRLSLDI", "RLWNM [$]12, R[0-9]+, [$]21, [$]28, R[0-9]+"547	b[0] = b[uint8(v>>23)]548	// ppc64x: -"CLRLSLDI", "RLWNM [$]15, R[0-9]+, [$]21, [$]28, R[0-9]+"549	b[1] = b[(v>>20)&0xFF]550	// ppc64x: "RLWNM", -"SLD"551	b[2] = b[((uint64((uint32(v) >> 21)) & 0x3f) << 4)]552	// ppc64x: -"RLWNM"553	b[3] = (b[3] << 24) & 0xFFFFFF000000554	// ppc64x: "RLWNM [$]24, R[0-9]+, [$]0, [$]7,"555	b[4] = (b[4] << 24) & 0xFF000000556	// ppc64x: "RLWNM [$]24, R[0-9]+, [$]0, [$]7,"557	b[5] = (b[5] << 24) & 0xFF00000F558	// ppc64x: -"RLWNM"559	b[6] = (b[6] << 0) & 0xFF00000F560	// ppc64x: "RLWNM [$]4, R[0-9]+, [$]28, [$]31,"561	b[7] = (b[7] >> 28) & 0xF562	// ppc64x: "RLWNM [$]11, R[0-9]+, [$]10, [$]15"563	c[0] = c[((v>>5)&0x3F)<<16]564	// ppc64x: "ANDCC [$]8064,"565	c[1] = c[((v>>7)&0x3F)<<7]566}567 568func checkShiftMask(a uint32, b uint64, z []uint32, y []uint64) {569	_ = y[128]570	_ = z[128]571	// ppc64x: -"MOVBZ", -"SRW", "RLWNM"572	z[0] = uint32(uint8(a >> 5))573	// ppc64x: -"MOVBZ", -"SRW", "RLWNM"574	z[1] = uint32(uint8((a >> 4) & 0x7e))575	// ppc64x: "RLWNM [$]25, R[0-9]+, [$]27, [$]29, R[0-9]+"576	z[2] = uint32(uint8(a>>7)) & 0x1c577	// ppc64x: -"MOVWZ"578	y[0] = uint64((a >> 6) & 0x1c)579	// ppc64x: -"MOVWZ"580	y[1] = uint64(uint32(b)<<6) + 1581	// ppc64x: -"MOVHZ", -"MOVWZ"582	y[2] = uint64((uint16(a) >> 9) & 0x1F)583	// ppc64x: -"MOVHZ", -"MOVWZ", -"ANDCC"584	y[3] = uint64(((uint16(a) & 0xFF0) >> 9) & 0x1F)585}586 587// 128 bit shifts588 589func check128bitShifts(x, y uint64, bits uint) (uint64, uint64) {590	s := bits & 63591	ŝ := (64 - bits) & 63592	// check that the shift operation has two commas (three operands)593	// amd64:"SHRQ.*,.*,"594	shr := x>>s | y<<ŝ595	// amd64:"SHLQ.*,.*,"596	shl := x<<s | y>>ŝ597	return shr, shl598}599 600func checkShiftToMask(u []uint64, s []int64) {601	// amd64:-"SHR" -"SHL" "ANDQ"602	u[0] = u[0] >> 5 << 5603	// amd64:-"SAR" -"SHL" "ANDQ"604	s[0] = s[0] >> 5 << 5605	// amd64:-"SHR" -"SHL" "ANDQ"606	u[1] = u[1] << 5 >> 5607}608 609//610// Left shift with addition.611//612 613func checkLeftShiftWithAddition(a int64, b int64) int64 {614	// riscv64/rva20u64: "SLLI" "ADD"615	// riscv64/rva22u64,riscv64/rva23u64: "SH1ADD"616	a = a + b<<1617	// riscv64/rva20u64: "SLLI" "ADD"618	// riscv64/rva22u64,riscv64/rva23u64: "SH2ADD"619	a = a + b<<2620	// riscv64/rva20u64: "SLLI" "ADD"621	// riscv64/rva22u64,riscv64/rva23u64: "SH3ADD"622	a = a + b<<3623	return a624}625 626//627// Convert and shift.628//629 630func rsh64Uto32U(v uint64) uint32 {631	x := uint32(v)632	// riscv64:"MOVWU"633	if x > 8 {634		// riscv64:"SRLIW" -"MOVWU" -"SLLI"635		x >>= 2636	}637	return x638}639 640func rsh64Uto16U(v uint64) uint16 {641	x := uint16(v)642	// riscv64:"MOVHU"643	if x > 8 {644		// riscv64:"SLLI" "SRLI"645		x >>= 2646	}647	return x648}649 650func rsh64Uto8U(v uint64) uint8 {651	x := uint8(v)652	// riscv64:"MOVBU"653	if x > 8 {654		// riscv64:"SLLI" "SRLI"655		x >>= 2656	}657	return x658}659 660func rsh64to32(v int64) int32 {661	x := int32(v)662	// riscv64:"MOVW"663	if x > 8 {664		// riscv64:"SRLIW" -"MOVW" -"SLLI"665		x >>= 2666	}667	return x668}669 670func rsh64to16(v int64) int16 {671	x := int16(v)672	// riscv64:"MOVH"673	if x > 8 {674		// riscv64:"SLLI" "SRLI"675		x >>= 2676	}677	return x678}679 680func rsh64to8(v int64) int8 {681	x := int8(v)682	// riscv64:"MOVB"683	if x > 8 {684		// riscv64:"SLLI" "SRLI"685		x >>= 2686	}687	return x688}689 690// We don't need to worry about shifting691// more than the type size.692// (There is still a negative shift test, but693// no shift-too-big test.)694func signedModShift(i int) int64 {695	// arm64:-"CMP" -"CSEL"696	return 1 << (i % 64)697}698