datasets
Training and evaluation data, with the modality, task and licence stated up front. Listed live from the Hugging Face Hub.
cross-hardware-reproducibility
Cross-hardware reproducibility of LLM evaluation results (item level)
Same model, same prompts, same decode settings, different machine: does each item get the same
answer? This dataset holds the item-level evidence behind the preprint "Same model, same prompts,
different answers: item-level cross-hardware reproducibility of LLM evaluation results"
(Nicholas Templeman, CSOAI Ltd (Council of AI), 2026). The PDF is in this repository:
paper/paper.pdf; its LaTeX source, with the… See the full description on the dataset page: https://huggingface.co/datasets/csoai/cross-hardware-reproducibility.hardware-cvdp-complete
CVDP - Comprehensive Verilog Design Problems (Complete Dataset)
🎯 782 out of 783 problems from the official CVDP benchmark by NVIDIA Research
🔥 Dataset Overview
This is the most complete version of the Comprehensive Verilog Design Problems (CVDP) benchmark available, containing 782 problems across 13 task categories. CVDP is designed to evaluate Large Language Models and agents on RTL design and verification tasks.
📊 Dataset Statistics
Total Problems: 772… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/hardware-cvdp-complete.hardware-cvdp-problems
Hardware Design AI Training Dataset
This dataset contains processed hardware design problems and Verilog code for training AI models.
Contents
CVDP Problems: 160 evaluation problems organized by domain and complexity
Training Data: Instruction-code pairs for hardware design
Metadata: Rich annotations for each problem
Usage
from datasets import load_dataset
dataset = load_dataset("AbiralArch/hardware-cvdp-problems")
Categories
Module Generation… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/hardware-cvdp-problems.embedded-hardware-cot
⚡ PyIntel Embedded Hardware CoT (The Hardware Architect)
Zero-hallucination physical constraint reasoning grounded directly in 1,717 microcontrollers and development boards.
pyintel/embedded-hardware-cot is a specialized chain-of-thought (CoT) reasoning dataset designed to teach LLMs how to solve strict physical, electrical, and computational constraints in embedded systems without hallucinating specs or recommending circuits that would fry real silicon.
Grounded in… See the full description on the dataset page: https://huggingface.co/datasets/pyintel/embedded-hardware-cot.hardware-verilogeval-v2
hardware-verilogeval-v2
VerilogEval v2 - 471 Verilog evaluation problems
Dataset Overview
This dataset is part of a comprehensive collection of hardware design datasets for training and evaluating LLMs on Verilog/SystemVerilog code generation and hardware design tasks.
Files
verilog_eval_problems.json: 471 VerilogEval v2 problems
Usage
from datasets import load_dataset
# Load the dataset
dataset = load_dataset('AbiralArch/hardware-verilogeval-v2')… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/hardware-verilogeval-v2.quantum-hardware-device-physics
Neura Parse — Quantum Hardware Device Physics: Qubit Design, Coherence, Control & Scaling
A physics- and engineering-deep vertical on how qubits are built, controlled, and scaled across superconducting, trapped-ion, neutral-atom, and spin modalities (plus emerging erasure/biased-noise qubits). Device-physics derivations, coherence-limit analyses, control-stack engineering, and 2025-2026 scaling/interconnect work, with QuTiP/scqubits simulation context — expanding the general… See the full description on the dataset page: https://huggingface.co/datasets/Neura-parse/quantum-hardware-device-physics.hardware-cvdp-examples
hardware-cvdp-examples
CVDP Example Problems - 5 comprehensive hardware design problems
Dataset Overview
This dataset is part of a comprehensive collection of hardware design datasets for training and evaluating LLMs on Verilog/SystemVerilog code generation and hardware design tasks.
Files
cvdp_problems.json: 5 CVDP example problems with full content
analysis.json: Analysis of CVDP problems
Usage
from datasets import load_dataset
# Load the… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/hardware-cvdp-examples.hardware-shailja-vgen
hardware-shailja-vgen
Shailja VGen Collection - 87 Verilog files
Dataset Overview
This dataset is part of a comprehensive collection of hardware design datasets for training and evaluating LLMs on Verilog/SystemVerilog code generation and hardware design tasks.
Files
vgen_files.json: 87 Verilog files from VGen framework
Usage
from datasets import load_dataset
# Load the dataset
dataset = load_dataset('AbiralArch/hardware-shailja-vgen')
# Access… See the full description on the dataset page: https://huggingface.co/datasets/AbiralArch/hardware-shailja-vgen.