IDEALLab/power_electronics_v0

This dataset is part of the EngiBench toolkit: https://github.com/IDEALLab/EngiBench.

Historical provenance and objective semantics

This is the original EngiBench PowerElectronics v0 dataset, retained unchanged for compatibility. Its 9,676 training, 2,765 validation, and 1,383 test rows and published labels have not been modified. The archived generation path applied absolute values to the signed ngspice gain and voltage-ripple outputs before storing DcGain and Voltage_Ripple. The v0 Python problem declares gain to be minimized and ripple to be maximized; these are historical API semantics, not the corrected objectives recommended for new work.

The exact original simulator environment cannot be confirmed. An archived notebook refers to a Windows ngspice.exe and an ngspice 36 manual, while a small reproduction using ngspice 44.2 on an ARM64 Mac is closer to these published labels than a corresponding Linux x86_64 reproduction. These are conflicting clues, not proof of the original CPU architecture. v0 does not store a complete simulator fingerprint, so installing a current ngspice build does not guarantee reproduction of its labels.

For new work, use the PowerElectronics v1 dataset and explicitly import from engibench.problems.power_electronics.v1 import PowerElectronics. v1 reuses the same designs and splits but is a new Linux x86_64/ngspice 44.2 benchmark with corrected minimization objectives, signed measurements, and per-row provenance. Do not silently combine v0 and v1 labels.