architect-ubc-capstone/rtl-augmented-v3
RTL Bug Fix — Augmented Dataset Auto-generated dashboard snapshot (2026-04-14T10:53:43). Overview Metric Value Total problems 718 Repos with data 57 / 81 Modules augmented 408 Bug types 11/11 Augmentation success 48.9% Coverage Distribution Augmentation Health Topic Coverage Warnings lucky-wfw_IC_System_Design: 0 problems from 48 attempts — likely systematic… See the full description on the dataset page: https://huggingface.co/datasets/architect-ubc-capstone/rtl-augmented-v3.
01.8k
RTL Bug Fix — Augmented Dataset
Auto-generated dashboard snapshot (2026-04-14T10:53:43).
Overview
Coverage
Distribution
Augmentation Health
Topic Coverage
Warnings
- lucky-wfwICSystem_Design: 0 problems from 48 attempts — likely systematic sim issue
- meiniKi_FazyRV: 0 problems from 8 attempts — likely systematic sim issue
- erihsuINTFP_MAC: 0 problems from 17 attempts — likely systematic sim issue
- semify-eda_go.debug: 0 problems from 14 attempts — likely systematic sim issue
- case_swap: underrepresented (29 problems, 4.0%)
- concat_swap: underrepresented (40 problems, 5.6%)
- offbyone_counter: underrepresented (13 problems, 1.8%)
- state_transition: underrepresented (32 problems, 4.5%)
- unconnected_port: underrepresented (42 problems, 5.8%)
- widthbitcutoff: underrepresented (6 problems, 0.8%)
- No augmentation data for topics: altera, chisel, core, dlx, fpga-soc, hardware-designs, microprocessor, mips, nuclei, processor, python, riscv64, rv32, simulation, soc, vlsi
- 49/81 discovered repos have zero augmentation data
